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Summary:

Manage an ASIC design team responsible for various processing blocks in a SOC. Drive RTL design planning and execution, innovative design methodology development, IP design and SOC integration. Participate in silicon architecture, micro-architecture development, interface with Architecture, SW/FW, Verification, Modelling, Emulation, and Post-Silicon Validation teams.

Required Skills:

Asic Design Engineering Manager Responsibilities:

1. Manage an ASIC design team responsible for various processing blocks in a SOC. Drive RTL design planning and execution, innovative design methodology development, u-Arch, IP design and SOC integration. Participate in silicon architecture, interface with Architecture, SW/FW, Design, Modelling, Emulation, and Post-Silicon Validation teams

2. Partner with internal and external cross-functional teams, across all levels of a corporation, from executives, team managers and individual contributors including development engineers, capacity planners and supply chain experts

3. Contribute to and drive development of and maintain overall silicon strategy aligned to corporation's Long Range Plan objectives

4. Collaborate with IP development teams, and participate in, and support soft and hard IP identification, selection and IP licensing

5. Build, lead, and support a team of ASIC engineers through strategic hiring, training, and guidance to drive on-time and on-budget product delivery

6. Contribute to, analyze, review SOWs from vendors, supporting documentation, requirements sets that meet the needs of internal customers

7. Support engineering teams to define, debug, implement and deliver total solutions around purpose built ASICs

8. Define, implement and maintain key performance indicators (KPI) for areas of responsibility

9. Partner with technical program management and supply chain team members to manage external development partners, suppliers and vendors

Minimum Qualifications:

Minimum Qualifications:

10. B.S. or M.S. degree in Computer Engineering or Electrical Engineering, relevant technical field, or equivalent practical experience

11. 12+ years experience in ASIC/SoC RTL design

12. 3+ years of experience as a People Manager

13. Clear understanding of complexities involved with various RTL design tools, including Synopsys DC compiler, Cadence LEC, Spyglass.

14. Track record of first-pass success in ASIC Development

15. Experience working across multiple projects and adjusting priorities in partnership with stakeholders

16. Experience with interpreting functional specs and creating comprehensive u-Arch

Preferred Qualifications:

Preferred Qualifications:

17. Hands-on experience with complex subsystems like memory/LPDDR/HBM, cache, PCIE or Network on chip.

18. In depth knowledge of at least one of these areas - NICs, signal processing algorithms, neural networks and machine learning concepts, and/or other neural network development framework

Industry: Internet