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Job Description

Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure highquality integration and verification of the IP block. Drives quality assurance compliance for smooth IPSoC handoff.

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• The candidate must possess a minimum of a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.

• 0-2 years of relevant logic design/pre-silicon verification experience with multiple project cycles.

• Advanced English level

• Costa Rican unrestricted work permit.

• 0-2 years of logic design/pre-silicon verification experience with various tools and methodologies including but not limited to: System Verilog, RTL simulators, VLSI or Structural and Physical design flow/methodology experience.

Preferred Qualifications:

• Testbench development

• Work experience with system Verilog or OVM or UVM or Object-Oriented Programming (OOP)

• Formal Equivalence Testing

• RTL model build

• Power-aware simulation

• Coverage-based random constraint simulation

• Capable in developing test plans, tests and verification environment based on High Level Architecture specifications.

• Power management, IOSF, AHB, PCI express or any industry standard BUS protocol experience a plus

• OVM / UVM

• Scripting (Python/Perl/Shell)

• Interactive debugger

Inside this Business Group

Corporate Strategy Office is chartered to support the executive office in driving corporate initiatives, including near and long-term strategy, major cross-group decision making and ensuring cross-company alignment. To deliver to that mission, the team owns shaping, driving and synthesizing insights to directionally orient trends as well as long range strategic planning/visioning , cross company alignment and greenfield innovation. Communications are essential to drive alignment so there is a focus on communications, community and acumen development. The team is ccommitted to ensuring that Intel efforts are aligned to, and actively driving success toward the most impactful business strategies.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.